1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof which are suitable for a non-volatile memory such as a NAND type EEPROM, etc., in which an element isolation insulation film is embedded to after depositing a gate electrode.
2. Description of the Background Art
An STI (Shallow Trench Isolation) technique has hitherto been known as an element isolation technique used for a high-integration memory such as a NAND type EEPROM, etc. The STI technique is that a shallow trench is formed in an element isolation region on a semiconductor substrate, and the shallow trench is filled with an element isolation insulation material.
The followings are specific methods to which the STI technique is applied:
(a) An element isolation insulation film is formed by embedding then a gate insulation layer and a gate electrode are sequentially formed in a device region.
(b) Agate insulation layer and a gate electrode layer are sequentially formed on the entire substrate, then the gate electrode layer, the gate insulation layer and the substrate are etched to dig a trench, then an insulating material is filled in the trench.
FIG. 1A is a plan view of a memory cell array area of the NAND type EEPROM, showing a state where the element isolation insulation film is embedded by applying the latter method, and FIG. 1B is a sectional view taken along the line Axe2x80x94A, thereof. As shown in FIGS. 1A and 1B, before embedding an element isolation insulation film 4, a gate electrode 6 serving as a part of a floating gate electrode and a silicon nitride layer 7 serving as a stopper mask material for a CMP process, are deposited on a silicon substrate 1 through a gate insulation film (tunnel electrode 6, the gate insulation film 5 and the substrate 1 are etched by RIE (Reactive Ion Etching) using a resist pattern, thereby forming a trench 3 in an element isolation region. The element isolation insulation film 4 is embedded in the trench 3. A striped device area 2 defined by the element isolation insulation film 4 is thereby provided. The element isolation insulation film 4 is embedded substantially flush with the silicon nitride layer 7. Hereafter, the silicon nitride layer 7 is removed, and a control gate electrode is provided by stacking it.
FIG. 2A is a plan view showing a state where a control gate electrode 9 is formed in a pattern, and FIG. 2B is a sectional view taken along the line Bxe2x80x94B, thereof. At a stage shown in FIG. 1B, the gate electrode 6 has been isolated, however, the isolation per memory transistor within the striped device area 2 is not yet done. After removing the silicon nitride layer 7, a gate electrode 6b composing a floating gate electrode is deposited together with the gate electrode 6, and a slit is formed in an element isolation region. Thereafter, an inter-layer gate insulting layer 8 is provided thereon, and a control gate electrode 9 is provided. In a process of patterning the control gate electrode 9, simultaneously the gate electrodes 6b, 6 are etched, thereby obtaining a floating gate electrode isolated per memory transistor in the device area 2.
According to the conventional manufacturing method, however, as shown in FIG. 2A, etching residuals 10 of the gate electrodes 6, 6b are produced along the boundary of the element isolation trench 3 between the patterned control gate electrodes 9. This is because if the element isolation insulation film 4 is as shown in FIG. 1B embedded in the trench formed by the RIE, the element isolation insulation film 4 takes, when removing the silicon nitride layer 7 thereafter, such a form of protruding in an inverted tapered shape above the gate electrode 6.
Namely, when patterning the control gate electrode 9 and subsequently etching the gate electrodes 6b, 6 in sequence, of the gate electrodes 6b, 6, especially the lower gate electrode 6, of which some areas are shadowed by corners of the element isolation film 4, is not therefore completely etched. These etching residuals 10 might cause a defect such as a floating gate short-circuit of the memory transistor in the NAND type cell.
The same kind of problem might occur in not only the NAND type EEPROM but also other types of transistor circuits using the similar element isolation technique.
Therefore, it is a primary object of the present invention to provide a semiconductor device and a manufacturing method to thereof which are capable of surely preventing a short-circuit between gate electrodes.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate; an element isolation insulation film embedded in a trench formed in the semiconductor substrate in a state of protruding from a surface of the semiconductor substrate; and a transistor provided on the semiconductor substrate; wherein said element isolation insulation film embedded in the trench has a recess at an upper edge corner thereof.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate; an element isolation insulation film embedded in a trench formed in the semiconductor substrate in a state of protruding from a surface of the semiconductor substrate; and a transistor provided on the semiconductor substrate, said transistor having a gate electrode formed through a gate insulation film before embedding the element isolation insulation film wherein an upper edge corner of the element isolation insulation film is selectively recessed.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
sequentially depositing a gate electrode and a mask layer on a semiconductor substrate through a gate insulation film;
forming a trench in an element isolation region by etching the gate electrode, the gate insulation film and the semiconductor substrate in sequence by anisotropic etching;
filling the element isolation insulation film in said trench substantially flush with the mask layer, with said mask layer remaining;
removing at least a part of the mask layer in a layer thickness wise direction thereof, and thereafter recessing an upper edge corner of the element isolation insulation film by isotropic etching; and
removing the mask layer and thereafter forming a gate electrode by patterning the gate electrode.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a memory cell array in which non-volatile memory transistors each including a floating gate electrode and a control gate electrode coupled in capacity thereto are formed in array, the method comprising the steps of:
sequentially depositing a gate electrode and a mask layer on a semiconductor substrate through a gate insulation film;
forming a trench in an element isolation region by etching the gate electrode, the gate insulation film and the semiconductor substrate in sequence by anisotropic etching;
filling said element isolation insulation film in said trench substantially flush with the mask layer, with the mask layer remaining;
removing at least a part of the mask layer in a layer thickness wise direction thereof, and thereafter recessing an upper edge corner of the element isolation insulation film by isotropic etching;
a step of removing the mask layer, and thereafter depositing a second gate electrode composing a floating gate electrode together with the first gate electrode;
forming a slit for isolating the second gate electrode in the element isolation insulation film;
a step of providing a control gate electrode on the second gate electrode through an inter-layer gate insulation film; and
forming the floating gate electrode of each of the memory transistors by patterning the second and first gate electrodes in self-alignment with the control gate electrode.
According to the present invention, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode. With this contrivance, there is obtained the semiconductor device exhibiting a high reliability with no defect such as a short-circuit of the gate electrode.